1. Field of the Invention
This disclosure generally relates to techniques for implementing off-chip caches for computer systems. More specifically, this disclosure relates to techniques for using a separate cache chip that is accessed using optical waveguides that connect directly to each cache bank.
2. Related Art
High instruction throughput in a processor typically involves rapid translation of virtual addresses and fast memory accesses. To achieve such throughput, the memory subsystem of the processor may include a number of specialized hardware structures, including multiple levels of caches. Such caching structures reduce the average latency of memory accesses.
Most workloads generally benefit from a larger cache size. However, in single-chip processor designs, the amount of space available for caches is limited by die size and the area required for the processor cores and other structures. Large caches also suffer from significant wire delays, which can lead to non-uniform access times for different cache banks or may require the use of optimized wires that consume more area and introduce additional routing complexity. Placing large caches on a separate chip reduces some area limitations, but off-chip electronic connections typically do not provide sufficient bandwidth for high-speed cache access.
Hence, what is needed are techniques for accessing caches without the above-described problems of existing cache designs.